The electronics industry has experienced an ever increasing demand for smaller and faster electronic devices which are simultaneously able to support a greater number of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). Thus far these goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and lowering associated costs. However, such scaling has also introduced increased complexity to the semiconductor manufacturing process. Thus, the realization of continued advances in semiconductor ICs and devices calls for similar advances in semiconductor manufacturing processes and technology.
As merely one example, scaling down of IC dimensions has been achieved by extending the usable resolution of a given lithography generation by the use of one or more resolution enhancement technologies (RETs), such as phase shift masks (PSMs), off-axis illumination (OAI), and optical proximity correction (OPC). RETs may be used to increase a lithography process window, for example by modification of mask layouts to compensate for processing limitations used in the manufacture of an IC and which manifest themselves as process technology nodes are scaled down. Without RETs, simple scaling down of layout designs used at larger nodes often results in inaccurate or poorly shaped features. For example, rounded corners on a device feature that is designed to have right-angle corners may become more pronounced and/or may become critically distorted at smaller technology nodes, preventing a device with such a distorted feature from performing as desired. Other examples of inaccurate or poorly shaped pattern features may include pinching, necking, bridging, dishing, erosion, metal line thickness variations, and/or other such characteristics that can directly affect device performance. One type of OPC technique includes inserting sub-resolution assist features (SRAFs) into a design layout to prevent inaccurate or poorly shaped features. As a general rule, SRAFs should be small enough so that an SRAF pattern on a mask is not transferred (i.e., printed) onto a substrate during lithographic exposure/development processes. However, larger SRAFs are desirable as they are known to provide better depth of focus (DoF), contrast, and process window than their smaller counterparts. Thus, in some examples, use of mask layouts including SRAFs may result in inadvertently printed SRAFs on the substrate. Thus, existing techniques have not proved entirely satisfactory in all respects.